Amiga 500 2MB Handwired FastRAM Expansion


Introduction:

Having owned an Amiga 500 for a few months I was getting quite familiar with the hardware side of it. I had recently refurbished a Zydec Superboard 1.5MB expansion board, recapped the motherboard, and added a further 512KB of ChipRAM to the unpopulated motherboard sockets.

I had considered creating some type of FastRAM expansion but using DRAM memory ICs required refresh circuitry which meant it would get complicated. Another option was to use SRAM memory that required no refresh cycles. After looking at the A500 schematics and 68000 datasheet it appeared that all the signals needed to use SRAM memory were present on the CPU’s pins. I could build the whole assembly on top of a spare CPU – if it did not work then the UNDO was to put the original CPU back in.

I had some spare 1Megabyte SRAMs left over from another project. These were 1M x 8bit. To use them in the Amiga I would need to stack a couple of them to get a 16bit wide data bus. A simple decoding circuit was needed to activate the SRAM memory when the CPU was looking in a certain memory window. As I was going to try for a 2Megabyte expansion the memory window would be 0x200000 to 0x3FFFFF.

This project was mostly a labour of love, mixed in with a bit of what-if and patience testing.


Build Instructions:

Gather The Parts!

To get this expansion built I needed:

1. Spare 68000 CPU
2. 2x “1M x 8bit” SRAMs
3. HC138 Decoder
4. Inverter IC
5. 2x 100nF Decoupling Capacitors
6. 47K Resistor
7. Two pin Header and Jumper
8. A lot of thin wire



SRAM Common Signals:
The two SRAM ICs share a lot of the signals so these were coupled together. As the SRAMs were mounted on top of each other the easiest way was to carefully bend the common pins toward each other and solder the link wire to the join.

The Commoned Signals are:
1. +5V
2. GND
3. A00 thru A19
4. /OE (Output Enable)
5. R/_W (Read / Write)
6. CE2 (Chip Enable)

Once the wires were soldered the joins were covered in adhesive to prevent them breaking off when handling the wires.
A 100nF capacitor was attached to the commoned +5V and GND pins.



CPU Connections:
The two SRAMs were mounted to the top of the CPU with a layer of double-sided adhesive foam to keep it in place.
The link wires were roughly laid out and connected to the corresponding CPU pin.

The Connections are:
1. CPU +5V and GND pins connect to commoned SRAM +5v and GND
2. CPU Address pins A01 thru A20 connect to the commoned SRAM A00 thru A19
3. SRAM commoned /OE pins connects to CPU GND
4. CPU R/_W pin connects to commoned SRAM R/_W
5. CPU Data pins D00 thru D07 connects to Low Byte SRAM D0 thru D7
6. CPU Data pins D08 thru D15 connects to High Byte SRAM D0 thru D7
7. CPU /LDS pin connects to Low Byte SRAM /CE1
8. CPU /HDS pin connects to High Byte SRAM /CE1



Decoder Circuit:
In order to get the extra memory working properly it needs to be told when to become active. This must happen when the CPU looks in the memory area 0x200000 thru 0x3FFFFF.
We can use the CPU address pins A21 thru A23 to check this. By using an HC138 decoder we can get a usable Chip Select signal.
The HC138 will output a LOW signal when (A21 is HIGH) and (A22 is LOW) and (A23 is LOW)

HC138 connections:
1. CPU GND to Pin 8 (Gnd)
2. CPU +5V to Pin 16 (Vcc)
3. CPU +5V to Pin 6 (G1)
4. CPU /AS to Pins 4+5 (G2A / G2B)
5. CPU A21 to Pin 1 (A)
6. CPU A22 to Pin 2 (B)
7. CPU A23 to Pin 3 (C)
8. HC138 Pin 14 (Y1) is the Chip Select signal output

The 100nF capacitor goes across the HC138 VCC + GND pins.



Invert the Chip Select:
Pin 14 (Y1) on the HC138 will activate LOW when the memory address is between 0x200000 thru 0x3FFFFF.
This output is the opposite of what we need because the Chip Select on the SRAMs (CE2) is Active High. To fix this a small Tiny Logic Invertor IC was used.

Tiny Logic Invertor connections:
1. HC138 GND (Pin 8) to Invertor GND (Pin 3)
2. HC138 Vcc (Pin 16) to Invertor Vcc (Pin 5)
3. HC138 Pin 14 (Y1 Output) to Invertor Pin 2 (Input)
4. Invertor Pin 4 (Output) connects to one pin on the 2-Way Header

Enable / Disable Jumper:

To allow the FastRAM expansion to be enabled or disabled a 2-way header is positioned in circuit after the invertor. With the jumper in place the Chip Select will connect to the SRAMs. With the jumper removed the signal will not reach the SRAMs. The SRAM CE2 signal is pulled to GND by a 47K resistor to keep them inactive when the jumper is removed.

Circuit Schematic:


Datasheet Downloads (PDF):
CPU – Motorola MC68000
SRAM – BS62LV8001EIP55
74HC138 Decoder
NC7SZ04 TinyLogic Invertor


Memory Test

Power On
With the FastRAM expansion now installed in the Amiga I was relieved that none of the magic smoke leaked out when the power was applied.

When Workbench booted up the extra memory was not being reported in the title bar. I assumed that something was wrong and needed to see if there was a way to read or write to it as a sanity check. I found a monitor program called “Amiga Monitor” by Timo Rossi. Using this I was able to write the string “Hello World” into the first part of the memory block:


The memory was actually working – it was my rookie mistake to assume the Amiga looks for extra FastRAM when it boots.
Any FastRAM expansion needs extra hardware to tell the Amiga it exists – a term known as AutoConfig FastRAM. Without this function the Amiga needs to be told the memory exists.

We can do this manually using the AutoAddRAM utility to search for memory and add it to the pool:



Boot Workbench:
When Workbench 1.3 boots it will now see the extra memory.
The screenshot below shows 3662576 bytes for FastRAM as I had a 1.5MB expansion in the trapdoor.



How Fast is Fast..?
With the FastRAM installed I can get an extra squirt of speed out of SYSINFO:

No FastRAM:


With FastRAM:



Hard Memory Tests:
Initially when I ran Keir Fraser’s SysTest memory test it did display a lot of bit errors in the FastRAM area.
The memory was failing badly when reading / writing patterns with 16 High / 16 Low bits.

The problem was that my wire used for the VCC and GND rails was too thin and the voltage drop was too much.
After beefing these rails up with additional wire the memory tests were 100%


And finally..
If you are thinking of creating this type of expansion for your A500 there is an easier way to get FastRAM.
At the time of writing there is an assembly sold on eBay that gives you 8MB of FastRAM and is the AutoConfig type so you do not need to run a utility like AutoAddRAM to active it.


// Document End

sector101

Leave a Reply

Your email address will not be published. Required fields are marked *